SH7261 datasheet(390/1348 Pages) RENESAS

390 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 358 of 1312

REJ09B0320-0200

11.6

Suspending, Restarting, and Stopping of DMA Transfer

11.6.1

Suspending and Restarting DMA Transfer

Transfer on all channels of the DMAC can be suspended by clearing the DMST bit in the DMA

activation control register (DMSCNT) to "0". Transfer on a specific channel can also be

suspended by clearing the DMA transfer enable bit (DEN) in DMA control register B

(DMCNTBn) for that channel.

If the DMST bit or the corresponding DEN bit is cleared to "0" while single operand transfer or

sequential operand transfer is in progress, transfer is suspended on completion of the current single

operand transfer regardless of the transfer mode (whether transfer is in cycle-stealing or pipelined

mode).

When transfer in the non-stop transfer condition is in progress, DMA transfer is not suspended and

continues to completion (until the byte counter reaches "0") even if the DMST bit or

corresponding DEN bit is cleared to "0".

To restart DMA transfer on a channel for which transfer has been suspended, set (to "1")

whichever of DMST and the corresponding DEN bit has been cleared.

11.6.2

Stopping DMA Transfer on Any Channel

To stop transfer on any channel, suspend transfer on that channel and then initialize the interior

state of the DMAC for that channel by setting the DMAC internal state clear bit (DSCLR) in the

corresponding DMA control register B (DMCNTBn). In this case, only the transfer state of the

DMAC internal circuits is initialized; the registers retain their values.

SH7261 Datasheet(PDF) 390 Page - Renesas Technology Corp