SH7261 datasheet(394/1348 Pages) RENESAS

394 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 362 of 1312

REJ09B0320-0200

If the DMA transfer is not done sequentially, the DMA request must be canceled within three

cycles after the end of single operand transfer.

(2)

Edge sense

When an edge sense is specified (STRG = "00" or "10"), the rising or falling edge of the DMA

request signal indicates a DMA request.

When the selected edge is detected, the DMA request bit (DREQ) in the DMA control register B

(DMCNTBn) is set to "1". After that, the value in the DMA request bit (DREQ) is retained

regardless of shifts in the level of the DMA request signal. After the DMA request has been

accepted and the DAM acknowledge signal output, the DMA request bit (DREQ) is automatically

cleared to "0".

Since DMA requests are internally retained for a channel in edge sense mode, further occurrences

of the selected edge of the DMA request signal are ignored since the DMA request bit (DREQ)

has already been set back to "1".

Figure 11.9 is an example of DMA request reception processing when an edge sense is selected.

Read

Write

Read

System clock

DMA state

DMA acknowledge

output

The DMA request bit is set on detection of the selected edge.

The DMA request is thus maintained despite further changes

in the level of the DMA request signal.

Start of single operand transfer

DMA request input

(falling edge sense)

DMA request bit

[Legend]

: Sampling point for DMA requests

The DMA request bit is set on detection of the selected edge.

The DMA request is thus maintained despite further changes

in the level of the DMA request signal.

When the DMA request is accepted, the DMA acknowledge

signal is activated and the DMA request bit is cleared.

Figure 11.9 Example of DMA Request Reception Processing

when an Edge Sense is Selected

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