 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7261 Datasheet(PDF) 397 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7261 Datasheet(HTML) 397 Page - Renesas Technology Corp |
|
|
397 / 1348 page  Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 365 of 1312 REJ09B0320-0200 CKIO DMA (S) DMA (D) DACT (SACT = 1, DACT = 0) DACT (SACT = 0, DACT = 0) DACT (SACT = 0, DACT = 1) DACK DACT (SACT = 1, DACT = 1) CKIO DMA (S) DMA (D) DACT (SACT = 1, DACT = 0) DACT (SACT = 0, DACT = 0) DACT (SACT = 0, DACT = 1) DACK DAC T (SACT = 1, DACT = 1) RD1 RD2 RD3 RD3 WR1 WR2 WR3 WR3 RD1 RD2 WR1 WR2 DMA (S): Internal cycles of source-side access by the DMAC DMA (D): Internal cycles of destination-side access by the DMAC [Legend] Cycle-stealing transfer mode Single operand transfer (read 0 wait) Single operand transfer (read 0 wait) Pipeline transfer mode High High Figure 11.11 Timing of DMA Acknowledge and DNA Active Signal Output |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
