SH7261 datasheet(396/1348 Pages) RENESAS

396 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 364 of 1312

REJ09B0320-0200

ch2DMA

ch3DMA

ch0DMA

ch2DMA

ch3DMA

ch0DMA

ch1DMA

ch3DMA

DMA request

(ch 1)

DMA request

(ch 2)

DMA receive

channel

Notes: 1. Channels 0, 2 and 3 are set to level sensing.

2. Channel 1 is set to edge sensing.

3. Thick lines indicate periods where the corresponding DREQ bits are set.

DMA request

(ch 0)

DMA request

(ch 3)

Masked period

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

Figure 11.10 Overall Operation during Multiple DMA Requests

11.8.3

Output of the DMA Acknowledge and DNA Active Signals

The settings of the DMA active signal output control bits for the source and destination (SACT or

DACT) in the corresponding DMA mode register control the output of the DMA active signal

(DACT) for a channel.

When SACT is set to 1, the DACT signal is activated in response to read access.

When DACT is set to 1, the DACT signal is activated in response to write access.

When both SACT and DACT are set to 1, the DACT signal is activated in response to read and

write access.

However, DACT signals are not activated for DMA requests from external peripheral circuits,

regardless of the setting of this bit.

The DMA acknowledge signal (DACK) is output throughout each single operand transfer.

Figure 11.11 is the timing chart for DMA acknowledge and DMA active signal output.

Note:

The BSC is provided with a write buffer. Writing data to this buffer while writing to the

external devices stops bus access in the chip. Because of this, in DMA transfer to or from

external devices, the DACT or DACK signal become disabled ("H") before the end of

external bus access. In this case, these signals are not synchronized with the external bus

access.

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