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SH7261 Datasheet(PDF) 389 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 389 Page - Renesas Technology Corp |
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389 / 1348 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 357 of 1312 REJ09B0320-0200 CKIO RD1 RD2 RD1 RD2 DMA (S) DMA (D) DTEND (00) DACK DMINT_N DTEND (01) DTEND (11) DTEND (10) WR1 WR2 WR1 WR2 High High CKIO DMA (S) DMA (D) DTEND (00) DACK DMINT_N DTEND (01) DTEND (11) DTEND (10) WR1 WR2 WR3 WR4 RD1 RD2 RD3 RD4 WR1 WR2 WR3 WR4 RD1 RD2 RD3 RD4 One DMA transfer One DMA transfer Single operand transfer (read 1 wait) Single operand transfer (read 1 wait) Single operand transfer (read 0 wait) Single operand transfer (read 0 wait) DTCM setting DTCM setting Last read of one DMA transfer Last write of one DMA transfer End of one DMA transfer Last read of one DMA transfer Last write of one DMA transfer End of one DMA transfer Cycle-stealing transfer mode Pipelined transfer mode DMA (S): Internal access cycle on DMAC source side DMA (D): Internal access cycle on DMAC destination side [Legend] Figure 11.5 Timing of DMA End Signal Output |
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