SH7261 datasheet(381/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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381 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 349 of 1312

REJ09B0320-0200

Table 11.5

List of DMA Transfer Conditions

DMA Transfer

Condition Select

Bits (DSEL)

DMA Transfer Condition

Remarks

DSEL

= "00"

Unit operand transfer

• The number of bytes selected for transfer in single

operand transfer (by the OPSEL bits) is transferred

in response to one DMA request.

• Channel arbitration is performed on completion of

each single operand transfer.

DSEL

= "01"

Sequential operand transfer

• Transfer in response to a DMA request proceeds in

unit transfer operations until the byte counter

reaches "0".

• Channel arbitration is performed on completion of

each single operand transfer.

DSEL

= "11"

Non-stop transfer

• Transfer in response to a DMA request proceeds

continuously until the byte counter reaches "0" by

one DMA request.

• Once transfer has started, channel arbitration is not

done until it is complete.

OPSEL bit is

disabled

SH7261 Datasheet(PDF) 381 Page - Renesas Technology Corp