SH7261 datasheet(375/1348 Pages) RENESAS

375 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 343 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

31 to 24 DEDET

All 0

R/W

Values read: DMA Transfer End Condition Detection

Values written: DMA Transfer End Condition

Detection, DMA Interrupt Request

Status Clear

These bits are used to verify the status of DMA

transfer end condition detection for each channel.

Reading this register does not automatically clear the

bits. Once a bit has been set to "1", the value is

retained in the register as long as the bit is not cleared

by software or a reset.

• Condition for setting to "1"

When the DMA transfer end condition is detected,

these bits are set to "1".

• Condition for clearing to "0"

These bits are cleared to "0" by writing a "1" to the

bits to be cleared. Write "0" to bits that are not to

be cleared. While a bit is clear, it cannot be set to

"1" by a write operation.

When the DMA transfer end interrupt is in use and an

interrupt request generated for a given channel starts

to be handled, write a "1" to the corresponding DMA

transfer end condition detection (DEDET) bit.

When the DMA transfer end condition detection

(DEDET) bits are cleared to "0", the DMA interrupt

request status bit (DISTS) is also cleared.

Values read:

0: DMA transfer end condition not detected

1: DMA transfer end condition detected

Values written:

0: Invalid

1: Clears DMA transfer end condition detection and

DMA interrupt request status

23 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel

1, …, 24: channel 7).

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