SH7261 datasheet(372/1348 Pages) RENESAS

372 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 340 of 1312

REJ09B0320-0200

11.3.12

DMA Common Interrupt Control Register (DMICNTA)

DMICNTA determines which channels contribute to the output of a common interrupt request

signal.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

R/W

RRRRRRRR

0000000000000000

RRRRRRRRRRRRRRRR

DINTA

—

—————————

Bit

Bit Name

Initial

Value

R/W

Description

31 to 24 DINTA

All 0

R/W

DMA Common Interrupt Request Signal Control

These bits are used to determine which channels

contribute to the output of a common interrupt request

signal.

Channels for which the DINTA bit is set to "1"

contribute to the output of a common interrupt request

signal.

Channels for which the DINTA bit is cleared to "0" do

not contribute to the output of a common interrupt

request signal.

Only the states of channels for which the

corresponding DINTA bit is set to "1" are reflected in

the DMA interrupt status register (DMISTS) when a

common interrupt request signal has been generated.

For details, see section 11.5.2, DMA Interrupt

Requests.

0: The channel does not contribute to the output of a

common interrupt requests

1: The channel contributes to the output of a common

interrupt request

23 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Note:

Bits 31 to 24 correspond to channel 0 to 7, respectively (31: channel 0, 30: channel

1, …, 24: channel 7).

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