SH7261 datasheet(364/1348 Pages) RENESAS

364 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 332 of 1312

REJ09B0320-0200

11.3.9

DMA Control Register B (DMCNTB)

DMCNTB enables or disables DMA transfer, clears the DMA transfer enable bit, and also clears

the internal state. In addition, this register can check the status of a DMA request.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRR

R/W

RRRRRRR

R/W

0000000000000000

RRRRRRR

R/W

RRRRRRR

R/W

—

DEN

DREQ

—

ECLR

DSCLR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 25



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DEN

R/W

DMA Transfer Enable

This bit is used to enable or disable DMA transfer on

the corresponding channel.

Clearing this bit to "0" disables DMA transfer.

Setting this bit to "1" enables DMA transfer. For the

activation of DMA transfer, see section 11.4.3, DMA

Activation.

Even when this bit is clear, the input of a DMA request

to the DMAC can change the value of the DMA

request bit (DREQ).

When the DMA transfer enable clear bit (ECLR) is set

to "1", this bit is automatically cleared to "0" on

detection of the DMA transfer end condition.

Clearing this bit to "0" during DNA transfer can be

used to stop channel operation at the end of the

current single operand transfer. For details, see

section 11.6, Suspending, Restarting, and Stopping of

DMA Transfer.

0: DMA transfer disabled

1: DMA transfer enabled

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