SH7261 datasheet(491/1348 Pages) RENESAS

491 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 459 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

WRE

R/(W)

Waveform Retain Enable

Selects the waveform output when synchronous

counter clearing occurs in complementary PWM mode.

The output waveform is retained only when

synchronous clearing occurs within the Tb interval at

the trough in complementary PWM mode. When

synchronous clearing occurs outside this interval, the

initial value specified in TOCR is output regardless of

the WRE bit setting. The initial value is also output

when synchronous clearing occurs in the Tb interval at

the trough immediately after TCNT_3 and TCNT_4 start

operation.

For the Tb interval at the trough in complementary

PWM mode, see figure 12.40.

0: Outputs the initial value specified in TOCR

1: Retains the waveform output immediately before

synchronous clearing

[Setting condition]

• When 1 is written to WRE after reading WRE = 0

Note:

Do not set to 1 when complementary PWM mode is not selected.

12.3.32

Bus Master Interface

The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle

buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR),

timer A/D converter start request control register (TADCR), timer A/D converter start request

cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers

(TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-

bit read/write is not possible. Always access in 16-bit units.

All registers other than the above registers are 8-bit registers. These are connected to the CPU by a

16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.

SH7261 Datasheet(PDF) 491 Page - Renesas Technology Corp

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