SH7261 datasheet(487/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 455 of 1312

REJ09B0320-0200

12.3.29

Timer Buffer Transfer Set Register (TBTER)

TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer

registers* used in complementary PWM mode to the temporary registers and specifies whether to

link the transfer with interrupt skipping operation. The MTU2 has one TBTER.

Bit:

Initial value:

R/W:

7654321

00000000

RRRRRR

R/W

—

BTE[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

7 to 2

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

1, 0

BTE[1:0]

R/W

These bits enable or disable transfer from the buffer

registers* used in complementary PWM mode to the

temporary registers and specify whether to link the

transfer with interrupt skipping operation.

For details, see table 12.42.

Note:

Applicable buffer registers:

TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR

SH7261 Datasheet(PDF) 487 Page - Renesas Technology Corp