SH7261 datasheet(484/1348 Pages) RENESAS

484 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 452 of 1312

REJ09B0320-0200

12.3.26

Timer Cycle Buffer Register (TCBR)

TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer

with the transfer timing set in the TMDR register.

The initial value of TCBR is H'FFFF.

Bit:

Initial value:

R/W:

1111111111111111

R/W

Note:

Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.

12.3.27

Timer Interrupt Skipping Set Register (TITCR)

TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and

specifies the interrupt skipping count. The MTU2 has one TITCR.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

T3AEN

3ACOR[2:0]

T4VEN

4VCOR[2:0]

Bit

Bit Name

Initial

value

R/W

Description

T3AEN

R/W

T3AEN

Enables or disables TGIA_3 interrupt skipping.

0: TGIA_3 interrupt skipping disabled

1: TGIA_3 interrupt skipping enabled

6 to 4

3ACOR[2:0] 000

R/W

These bits specify the TGIA_3 interrupt skipping count

within the range from 0 to 7.*

For details, see table 12.40.

T4VEN

R/W

T4VEN

Enables or disables TCIV_4 interrupt skipping.

0: TCIV_4 interrupt skipping disabled

1: TCIV_4 interrupt skipping enabled

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