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SH7261 Datasheet(PDF) 480 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 480 Page - Renesas Technology Corp

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 448 of 1312
REJ09B0320-0200
Set bit TOCS
Set TOCR2
Set TOLBR
[1]
[2]
[3]
[1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting.
[2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer
transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P
to specify the PWM output levels.
[3] The TOLBR initial setting must be the same value as specified in
bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
Figure 12.3 PWM Output Level Setting Procedure in Buffer Operation
12.3.22
Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Bit:
Initial value:
R/W:
7654321
0
10000000
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
BDC
N
P
FB
WF
VF
UF
Bit
Bit Name
Initial
value
R/W
Description
7
—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
6
BDC
0
R/W
Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective



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