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SH7261 Datasheet(PDF) 509 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 509 Page - Renesas Technology Corp |
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509 / 1348 page ![]() Section 12 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 Sep. 07, 2007 Page 477 of 1312 REJ09B0320-0200 (5) Cascaded Operation Example (d) Figure 12.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1. TCNT_2 value H'0000 H'0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H'0513 H'0512 H'0513 H'D000 H'FFFF H'D000 TCNT_0 value Time TGRA_0 Compare match between TCNT_0 and TGRA_0 Figure 12.24 Cascaded Operation Example (d) |
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