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SH7261 Datasheet(PDF) 508 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 508 Page - Renesas Technology Corp |
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508 / 1348 page  Section 12 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 Sep. 07, 2007 Page 476 of 1312 REJ09B0320-0200 (4) Cascaded Operation Example (c) Figure 12.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H'0514 H'0514 H'0513 H'0512 H'0513 H'0512 H'C256 H'C256 H'FFFF H'6128 H'6128 H'2064 H'2064 H'9192 H'9192 Figure 12.23 Cascaded Operation Example (c) |
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