SH7261 datasheet(505/1348 Pages) RENESAS

505 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 473 of 1312

REJ09B0320-0200

12.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 counter clock upon overflow/underflow of

TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 12.44 shows the register combinations used in cascaded operation.

Note:

When phase counting mode is set for channel 1, the counter clock setting is invalid and the

counters operates independently in phase counting mode.

Table 12.44 Cascaded Combinations

Combination

Upper 16 Bits

Lower 16 Bits

Channels 1 and 2

TCNT_1

TCNT_2

For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional

input capture input pins can be specified by the input capture control register (TICCR). For input

capture in cascade connection, refer to section 12.7.22, Simultaneous Capture of TCNT_1 and

TCNT_2 in Cascade Connection.

Table 12.45 show the TICCR setting and input capture input pins.

Table 12.45 TICCR Setting and Input Capture Input Pins

Target Input Capture

TICCR Setting

Input Capture Input Pins

I2AE bit = 0 (initial value)

TIOC1A

Input capture from TCNT_1 to

TGRA_1

I2AE bit = 1

TIOC1A, TIOC2A

I2BE bit = 0 (initial value)

TIOC1B

Input capture from TCNT_1 to

TGRB_1

I2BE bit = 1

TIOC1B, TIOC2B

I1AE bit = 0 (initial value)

TIOC2A

Input capture from TCNT_2 to

TGRA_2

I1AE bit = 1

TIOC2A, TIOC1A

I1BE bit = 0 (initial value)

TIOC2B

Input capture from TCNT_2 to

TGRB_2

I1BE bit = 1

TIOC2B, TIOC1B

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