SH7261 datasheet(535/1348 Pages) RENESAS

535 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 503 of 1312

REJ09B0320-0200

(g)

PWM Cycle Setting

In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which

the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set.

The settings should be made so as to achieve the following relationship between these two

registers:

With dead time: TGRA_3 set value = TCDR set value + TDDR set value

Without dead time: TGRA_3 set value = TCDR set value + 1

The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and

TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and

TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode

The updated PWM cycle is reflected from the next cycle when the data update is performed at the

crest, and from the current cycle when performed in the trough. Figure 12.42 illustrates the

operation when the PWM cycle is updated at the crest.

See the following section, Register Data Updating, for the method of updating the data in each

buffer register.

Counter value TGRC_3

update

TGRA_3

update

TGRA_3

TCNT_3

TCNT_4

Time

Figure 12.42 Example of PWM Cycle Updating

SH7261 Datasheet(PDF) 535 Page - Renesas Technology Corp