SH7261 datasheet(538/1348 Pages) RENESAS

538 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 506 of 1312

REJ09B0320-0200

(i)

Initial Output in Complementary PWM Mode

In complementary PWM mode, the initial output is determined by the setting of bits OLSN and

OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P

in timer output control register 2 (TOCR2).

This initial output is the PWM pulse non-active level, and is output from when complementary

PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in

the dead time register (TDDR). Figure 12.44 shows an example of the initial output in

complementary PWM mode.

An example of the waveform when the initial PWM duty value is smaller than the TDDR value is

shown in figure 12.45.

Timer output control register settings

OLSN bit: 0 (initial output: high; active level: low)

OLSP bit: 0 (initial output: high; active level: low)

TCNT_3 and TCNT_4 values

TGRA_4

TDDR

TCNT_3

TCNT_4

Initial output

Dead time

Time

Active level

TCNT_3 and TCNT_4 count start

(TSTR setting)

Complementary

PWM mode

(TMDR setting)

Positive phase

output

Negative phase

output

Figure 12.44 Example of Initial Output in Complementary PWM Mode (1)

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