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SH7261 Datasheet(PDF) 558 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 558 Page - Renesas Technology Corp

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 526 of 1312
REJ09B0320-0200
Buffer register
Temporary register
General register
TCNT_3
TCNT_4
Data1
Data2
Data*
Data2
Data*
Data2
(1)
(2)
(3)
Buffer transfer is suppressed
Note: * When buffer transfer at the crest is selected.
data1
Bit BTE1 in TBTER
Bit BTE0 in TBTER
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period
(bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively).
(2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period.
(3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register.
[Legend]
Figure 12.70 Example of Operation when Buffer Transfer is Suppressed
(BTE1 = 0 and BTE0 = 1)



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