SH7261 datasheet(668/1348 Pages) RENESAS

668 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 636 of 1312

REJ09B0320-0200

14.5

Usage Notes

Pay attention to the following points when using the WDT in either the interval timer or watchdog

timer mode.

14.5.1

Timer Variation

After timer operation has started, the period from the power-on reset point to the first count up

timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The

shortest such time period is thus one cycle of the peripheral clock, P

φ, while the longest is the

result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent

incrementation is in accord with the selected frequency division ratio. Accordingly, this time

difference is referred to as timer variation.

This also applies to the timing of the first incrementation after WTCNT has been written to during

timer operation.

14.5.2

Prohibition against Setting H'FF to WTCNT

When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred.

Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur

immediately, regardless of the current clock selection by the CKS[2:0] bits.

14.5.3

System Reset by

WDTOVF Signal

If the

WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.

Avoid input of the

WDTOVF signal to the RES pin of this LSI through glue logic circuits. To

reset the entire system with the

WDTOVF signal, use the circuit shown in figure 14.6.

RES

WDTOVF

Reset input

Reset signal to entire system

(low active)

Figure 14.6 Example of System Reset Circuit Using

WDTOVF Signal

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