SH7261 datasheet(664/1348 Pages) RENESAS

664 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 632 of 1312

REJ09B0320-0200

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Writing to WRCSR

WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte

transfer or longword transfer instructions.

Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are

different, as shown in figure 14.3.

To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower

byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the

RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The

values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.

The WOVF bit is not affected.

Address: H'FFFE0004

H'A5

H'00

H'5A

Writing 0 to the WOVF bit

Writing to the RSTE and RSTS bits

Write data

Figure 14.3 Writing to WRCSR

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Reading from WTCNT, WTCSR, and WRCSR

WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is

allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address

H'FFFE0004. Byte transfer instructions must be used for reading from these registers.

SH7261 Datasheet(PDF) 664 Page - Renesas Technology Corp