SH7261 datasheet(662/1348 Pages) RENESAS

662 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 630 of 1312

REJ09B0320-0200

14.3.3

Watchdog Reset Control/Status Register (WRCSR)

WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal

generated by watchdog timer counter (WTCNT) overflow.

WRCSR is initialized to H'1F by input of a reset signal from the

RES pin or in deep standby

mode, but is not initialized by the internal reset signal generated by overflow of the WDT.

WRCSR is initialized to H'1F in software standby mode.

Note:

The method for writing to WRCSR differs from that for other registers to prevent

erroneous writes. See section 14.3.4, Notes on Register Access, for details.

—

RSTS

RSTE

WOVF

11111

R/W

R/(W)

Bit:

Initial value:

R/W:

Bit

Bit Name

Initial

Value

R/W

Description

WOVF

R/(W)

Watchdog Timer Overflow

Indicates that the WTCNT has overflowed in

watchdog timer mode. This bit is not set in interval

timer mode.

0: No overflow

1: WTCNT has overflowed in watchdog timer mode

[Clearing condition]

• When 0 is written to WOVF after reading WOVF

RSTE

R/W

Reset Enable

Selects whether to generate a signal to reset the LSI

internally if WTCNT overflows in watchdog timer

mode. In interval timer mode, this setting is ignored.

0: Not reset when WTCNT overflows*

1: Reset when WTCNT overflows

Note: *

LSI not reset internally, but WTCNT and

WTCSR reset within WDT.

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