SH7261 datasheet(661/1348 Pages) RENESAS

661 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 629 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

TME

R/W

Timer Enable

Starts and stops timer operation. Clear this bit to 0

when using the WDT in software standby mode or

when changing the clock frequency.

0: Timer disabled

Count-up stops and WTCNT value is retained

1: Timer enabled

4, 3



All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

Clock Select

These bits select the clock to be used for the WTCNT

count from the eight types obtainable by dividing the

peripheral clock (P

φ). The overflow period that is

shown inside the parenthesis in the table is the value

when the peripheral clock (P

φ) is 25 MHz.

Bits 2 to 0

Clock Ratio

Overflow Cycle

000:

× Pφ

10.2

µs

001:

1/64

× Pφ

655.4

µs

010:

1/128

× Pφ

1.3 ms

011:

1/256

× Pφ

2.6 ms

100:

1/512

× Pφ

5.2 ms

101:

1/1024

× Pφ

10.5 ms

110:

1/4096

× Pφ

41.9 ms

111:

1/16384

× Pφ

167.8 ms

2 to 0

CKS[2:0]

000

R/W

Note: If bits CKS[2:0] are modified when the WDT is

running, the up-count may not be performed

correctly. Ensure that these bits are modified

only when the WDT is not running.

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