SH7261 datasheet(657/1348 Pages) RENESAS

657 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 625 of 1312

REJ09B0320-0200

Section 14 Watchdog Timer (WDT)

This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal

(

WDTOVF) on overflow of the counter when the value of the counter has not been updated

because of a system malfunction. The WDT can simultaneously generate an internal reset signal

for the entire LSI.

The WDT is a single channel timer that counts up the clock oscillation settling period when the

system leaves software standby mode or the temporary standby periods that occur when the clock

frequency is changed. It can also be used as a general watchdog timer or interval timer.

14.1

Features

• Can be used to ensure the clock oscillation settling time

The WDT is used in leaving software standby mode or the temporary standby periods that

occur when the clock frequency is changed.

• Can switch between watchdog timer mode and interval timer mode.

• Outputs WDTOVF signal in watchdog timer mode

When the counter overflows in watchdog timer mode, the

WDTOVF signal is output

externally. It is possible to select whether to reset the LSI internally when this happens. Either

the power-on reset or manual reset signal can be selected as the internal reset type.

• Interrupt generation in interval timer mode

An interval timer interrupt is generated when the counter overflows.

• Choice of eight counter input clocks

Eight clocks (P

φ × 1 to Pφ × 1/16384) that are obtained by dividing the peripheral clock can be

selected.

SH7261 Datasheet(PDF) 657 Page - Renesas Technology Corp