SH7261 datasheet(653/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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653 / 1348 page

Section 13 8-Bit Timers (TMR)

Rev. 2.00 Sep. 07, 2007 Page 621 of 1312

REJ09B0320-0200

13.8.3

Conflict between TCNT Write and Increment

If a TCNT input clock pulse is generated during the T

2 state of a TCNT write cycle, the write takes

priority and the counter is not incremented as shown in figure 13.13.

Address

TCNT address

Internal write signal

TCNT input clock

TCNT

TCNT write cycle by CPU

Counter write data

Figure 13.13 Conflict between TCNT Write and Increment

13.8.4

Conflict between TCOR Write and Compare Match

If a compare match event occurs during the T

2 state of a TCOR write cycle, the TCOR write takes

priority and the compare match signal is inhibited as shown in figure 13.14.

Address

TCOR address

Internal write signal

TCNT

TCOR

TCOR write cycle by CPU

TCOR write data

N + 1

Compare match signal

Inhibited

Figure 13.14 Conflict between TCOR Write and Compare Match

SH7261 Datasheet(PDF) 653 Page - Renesas Technology Corp