SH7261 datasheet(660/1348 Pages) RENESAS

660 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 628 of 1312

REJ09B0320-0200

14.3.2

Watchdog Timer Control/Status Register (WTCSR)

WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the

count, overflow flags, and timer enable bit.

WTCSR is initialized to H'18 by a power-on reset caused by the

RES pin or in deep standby mode

or software standby mode. When used to count the clock oscillation settling time for canceling

software standby mode, it retains its value after counter overflow.

Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from

WTCSR.

Note:

The method for writing to WTCSR differs from that for other registers to prevent

erroneous writes. See section 14.3.4, Notes on Register Access, for details.

R/W

R/(W)

R/W

Bit:

Initial value:

R/W:

IOVF WT/

IT TME

—

CKS[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

IOVF

R/(W)

Interval Timer Overflow

Indicates that WTCNT has overflowed in interval timer

mode. This flag is not set in watchdog timer mode.

0: No overflow

1: WTCNT overflow in interval timer mode

[Clearing condition]

• When 0 is written to IOVF after reading IOVF

WT/

R/W

Timer Mode Select

Selects whether to use the WDT as a watchdog timer

or an interval timer.

0: Use as interval timer mode

1: Use as watchdog timer mode

Note: When the WTCNT overflows in watchdog timer

mode, the

WDTOVF signal is output externally.

If this bit is modified when the WDT is running,

the up-count may not be performed correctly.

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