SH7261 datasheet(663/1348 Pages) RENESAS

663 / 1348 page

Section 14 Watchdog Timer (WDT)

Rev. 2.00 Sep. 07, 2007 Page 631 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

RSTS

R/W

Reset Select

Selects the type of reset when the WTCNT overflows

in watchdog timer mode. In interval timer mode, this

setting is ignored.

0: Power-on reset

1: Manual reset

4 to 0



All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

14.3.4

Notes on Register Access

The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and

watchdog reset control/status register (WRCSR) are more difficult to write to than other registers.

The procedures for reading or writing to these registers are given below.

(1)

Writing to WTCNT and WTCSR

These registers must be written by a word transfer instruction. They cannot be written by a byte or

longword transfer instruction.

When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,

as shown in figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the

lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or

WTCSR.

H'5A

H'A5

Write data

Address: H'FFFE0002

WTCNT write

Write data

Address: H'FFFE0000

WTCSR write

Figure 14.2 Writing to WTCNT and WTCSR

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