SH7261 datasheet(702/1348 Pages) RENESAS

702 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 670 of 1312

REJ09B0320-0200

• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and

receive-error interrupts are requested independently.

• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving

power.

• The quantity of data in the transmit and receive FIFO registers and the number of receive

errors of the receive data in the receive FIFO register can be ascertained.

• A time-out error (DR) can be detected when receiving in asynchronous mode.

Figure 16.1 shows a block diagram of the SCIF.

SCFRDR (16 stage)

SCFTDR (16 stage)

SCRSR

SCTSR

SCSMR

SCLSR

SCFDR

SCFCR

SCFSR

SCSCR

SCSPTR

SCBRR

TXI

RXI

ERI

BRI

φ/4

φ/16

φ/64

SCK

TxD

RxD

SCIF

Module data bus

Parity generation

Parity check

Transmission/reception

control

Baud rate

generator

Clock

External clock

Peripheral

bus

SCRSR:

SCFRDR:

SCTSR:

SCFTDR:

SCSMR:

SCSCR:

[Legend]

SCFSR:

SCBRR:

SCSPTR:

SCFCR:

SCFDR:

SCLSR:

Receive shift register

Receive FIFO data register

Transmit shift register

Transmit FIFO data register

Serial mode register

Serial control register

Serial status register

Bit rate register

Serial port register

FIFO control register

FIFO data count register

Line status register

Figure 16.1 Block Diagram of SCIF

SH7261 Datasheet(PDF) 702 Page - Renesas Technology Corp

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