SH7261 datasheet(703/1348 Pages) RENESAS

703 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 671 of 1312

REJ09B0320-0200

16.2

Input/Output Pins

Table 16.1 shows the pin configuration of the SCIF.

Table 16.1

Pin Configuration

Channel

Pin Name

Symbol

I/O

Function

Serial clock pins

SCK0 to SCK7

I/O

Clock I/O

Receive data pins

RxD0 to RxD7

Input

Receive data input

0 to 7

Transmit data pins

TxD0 to TxD7

Output

Transmit data output

16.3

The SCIF has the following registers.

Table 16.2

Channel

Abbreviation

R/W

Initial Value Address

Access

Size

Serial mode register_0

SCSMR_0

R/W

H'0000

H'FFFE8000

Bit rate register_0

SCBRR_0

R/W

H'FF

H'FFFE8004

Serial control register_0

SCSCR_0

R/W

H'0000

H'FFFE8008

Transmit FIFO data register_0

SCFTDR_0

Undefined

H'FFFE800C

Serial status register_0

SCFSR_0

R/(W)*

H'0060

H'FFFE8010

Receive FIFO data register_0

SCFRDR_0

Undefined

H'FFFE8014

FIFO control register_0

SCFCR_0

R/W

H'0000

H'FFFE8018

FIFO data count register_0

SCFDR_0

H'0000

H'FFFE801C

Serial port register_0

SCSPTR_0

R/W

H'0050

H'FFFE8020

Line status register_0

SCLSR_0

R/(W)*

H'0000

H'FFFE8024

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