SH7261 datasheet(835/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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835 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 803 of 1312

REJ09B0320-0200

(1)

Reception Using DMA Controller

Start

Enable SSI module,

enable DMA,

enable error interrupts.

Wait for interrupt from DMAC or SSI

SSI error interrupt?

More data to be send?

Disable SSI module,

disable DMA,

disable error interrupts,

enable Idle interrupt.

Wait for idle interrupt

from SSI module.

End*

Yes

EN = 1,

DMEN = 1,

UIEN = 1, OIEN = 1

EN = 0,

DMEN = 0

UIEN = 0, OIEN = 0,

IIEN = 1

Setup DMA controller

to transfer data

from SSI module to memory.

Release from reset,

define SSICR configuration bits.

DMAC:

End of Rx data?

Define TRMD, EN, SCKD, SWSD,

MUEN, DEL, PDTA, SDTA, SPDP,

SWSP, SCKP, SWL, DWL, CHNL.

Note: *

If the SSI encounters an error interrupt underflow/overflow,

go back to the start in the flowchart again.

Figure 18.22 Reception Using DMA Controller

SH7261 Datasheet(PDF) 835 Page - Renesas Technology Corp

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