SH7261 datasheet(831/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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831 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 799 of 1312

REJ09B0320-0200

18.4.4

Transmit Operation

Transmission can be controlled either by DMA or interrupt.

DMA control is preferred to reduce the processor load. In DMA control mode the processor will

only receive interrupts if there is an underflow or overflow of data or the DMAC has finished its

transfer.

The alternative method is using the interrupts that the SSI module generates to supply data as

required. This mode has a higher interrupt load as the module is only double buffered and will

require data to be written at least every system word period.

When disabling the module, the SSI clock* must remain present until the SSI module is in idle

state, indicated by the IIRQ bit.

Figure 18.20 shows the transmit operation in DMA control mode, and figure 18.21 shows the

transmit operation in interrupt control mode.

Note: * Input clock from the SSISCK pin when SCKD = 0.

Input clock from the AUDIO_CLK pin, or AUDIO_X1 and AUDIO_X2 pins when

SCKD = 1.

SH7261 Datasheet(PDF) 831 Page - Renesas Technology Corp