SH7261 datasheet(874/1348 Pages) RENESAS

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 842 of 1312

REJ09B0320-0200

Bit 0 – Reset/Halt/Sleep Interrupt Flag (IRR0): This flag can get set for three different reasons.

It can indicate that:

1. Reset mode has been entered after a SW (MCR0) or HW reset

2. Halt mode has been entered after a Halt request (MCR1)

3. Sleep mode has been entered after a sleep request (MCR5) has been made while in Halt mode.

The GSR may be read after this bit is set to determine which state RCAN-ET is in.

Important: When a Sleep mode request needs to be made, the Halt mode must be used

beforehand. Please refer to the MCR5 description and figure 19.8.

IRR0 is set by the transition from "0" to "1" of GSR3 or GSR4 or by transition from Halt mode to

Sleep mode. So, IRR0 is not set if RCAN-ET enters Halt mode again right after exiting from Halt

mode, without GSR4 being cleared. Similarly, IRR0 is not set by direct transition from Sleep

mode to Halt Request. At the transition from Halt/Sleep mode to Transition/Reception, clearing

GSR4 needs (one-bit time - TSEG2) to (one-bit time * 2 - TSEG2).

In the case of Reset mode, IRR0 is set, however, the interrupt to the CPU is not asserted since

IMR0 is automatically set by initialisation.

Bit 0: IRR0

Description

[Clearing condition] Writing 1

Transition to S/W reset mode or transition to halt mode or transition to sleep

mode (Initial value)

[Setting condition] When reset/halt/sleep transition is completed after a reset

(MCR0 or HW) or Halt mode (MCR1) or Sleep mode (MCR5) is requested

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