SH7261 datasheet(876/1348 Pages) RENESAS

876 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 844 of 1312

REJ09B0320-0200

19.4.6

Transmit Error Counter (TEC) and Receive Error Counter (REC)

The Transmit Error Counter (TEC) and Receive Error Counter (REC) is a 16-bit read/(write)

CAN Interface. The count value is stipulated in the CAN protocol specification Refs. [2], [3], [4]

and [5]. When not in (Write Error Counter) test mode this register is read only, and can only be

modified by the CAN Interface. This register can be cleared by a Reset request (MCR0) or

entering to bus off.

In Write Error Counter test mode (i.e. TST[2:0] = B'100), it is possible to write to this register.

The same value can only be written to TEC/REC, and the value written into TEC is set to TEC

and REC. When writing to this register, RCAN-ET needs to be put into Halt Mode. This feature is

only intended for test purposes.

• TEC/REC (Address = H'00C)

Bit:

Initial value:

R/W:

0000000000000000

R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

Note: * It is only possible to write the value in test mode when TST[2:0] in MCR is B'100.

REC is incremented during Bus Off to count the recurrences of 11 recessive bits as

requested by the Bus Off recovery sequence.

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