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SH7261 Datasheet(PDF) 875 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 875 Page - Renesas Technology Corp

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Rev. 2.00 Sep. 07, 2007 Page 843 of 1312
REJ09B0320-0200
19.4.5
Interrupt Mask Register (IMR)
The interrupt mask register is a 16-bit register that protects all corresponding interrupts in the
Interrupt Request Register (IRR) from generating an output signal on the IRQ. An interrupt
request is masked if the corresponding bit position is set to '1'. This register can be read or written
at any time. The IMR directly controls the generation of IRQ, but does not prevent the setting of
the corresponding bit in the IRR.
• IMR (Address = H'00A)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1111111111111111
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IMR15 IMR14 IMR13 IMR12 IMR11 IMR10
IMR9
IMR8
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1
IMR0
Bit 15 to 0: Maskable interrupt sources corresponding to IRR[15:0] respectively. When a bit is
set, the interrupt signal is not generated, although setting the corresponding IRR bit is still
performed.
Bit[15:0]: IMRn
Description
0
Corresponding IRR is not masked (IRQ is generated for interrupt conditions)
1
Corresponding interrupt of IRR is masked (Initial value)



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