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SH7261 Datasheet(PDF) 905 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 905 Page - Renesas Technology Corp

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Rev. 2.00 Sep. 07, 2007 Page 873 of 1312
REJ09B0320-0200
19.9.5
Interrupts
As shown in table 19.2, the Mailbox 0 receive interrupt enables the DMAC activation. When an
interrupt is specified as to be activated by the Mailbox 0 receive interrupt and cleared by the
interrupt source at the DMA transfer, up to the message control field 1 (CONTROL1) of Mailbox
0 should be read using the block transfer mode.



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