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SH7261 Datasheet(PDF) 902 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 902 Page - Renesas Technology Corp

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Rev. 2.00 Sep. 07, 2007 Page 870 of 1312
REJ09B0320-0200
Channel
Interrupt
Description
Interrupt
Flag
DTC
Activation
Error Passive Mode (TEC
≥ 128 or REC ≥ 128)
IRR5
Bus Off (TEC
≥ 256)/Bus Off recovery
IRR6
Error warning (TEC
≥ 96)
IRR3
ERS_1
Error warning (REC
≥ 96)
IRR4
Message error detection
IRR13*
1
Reset/halt/CAN sleep transition
IRR0
Overload frame transmission
IRR7
Unread message overwrite (overrun)
IRR9
OVR_1
Detection of CAN bus operation in CAN sleep
mode
IRR12
SLE_1
Message transmission/transmission disabled
(slot empty)
IRR8
RM1_1*
2
Not
possible
1
RM0_1*
2
Data frame reception/
Remote frame reception
IRR1*
3
IRR2*
3
Possible
Notes: 1. Available only in Test Mode.
2. RM0 is an interrupt generated by the remote request pending flag for mailbox 0
(RFPR0[0]) or the data frame receive flag for mailbox 0 (RXPR0[0]). RM1 is an interrupt
generated by the remote request pending flag for mailbox n (RFPR0[n]) or the data
frame receive flag for mailbox n (RXPR0[n]) (n = 1 to 15).
3.
IRR1 is a data frame received interrupt flag for mailboxes 0 to 15, and IRR2 is a
remote frame request interrupt flag for mailboxes 0 to 15.



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