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SH7261 Datasheet(PDF) 148 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 148 Page - Renesas Technology Corp |
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148 / 1348 page ![]() Section 5 Exception Handling Rev. 2.00 Sep. 07, 2007 Page 116 of 1312 REJ09B0320-0200 Exception Type Stack Status Register bank error (underflow) 32 bits 32 bits SR Start address of relevant RESBANK instruction SP Trap instruction 32 bits 32 bits SR Address of instruction after TRAPA instruction SP Slot illegal instruction 32 bits 32 bits SR Jump destination address of delayed branch instruction SP General illegal instruction 32 bits 32 bits SR Start address of general illegal instruction SP Integer division instruction 32 bits 32 bits SR Start address of relevant integer division instruction SP |
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