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SH7261 Datasheet(PDF) 151 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 151 Page - Renesas Technology Corp |
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151 / 1348 page  Section 6 Interrupt Controller (INTC) Rev. 2.00 Sep. 07, 2007 Page 119 of 1312 REJ09B0320-0200 Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 6.1 Features • 16 levels of interrupt priority can be set By setting the 14 interrupt priority registers, the priorities of the IRQ, PINT, and on-chip peripheral module interrupts can be set to one of 16 levels for each source. • NMI noise canceller function This controller provides an NMI input level bit that indicates the NMI pin state. The interrupt exception service routine can verify the pin state by reading this bit and use the information to implement a noise canceling function. • Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. Figure 6.1 shows a block diagram of the INTC. |
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