SH7619 datasheet(39/836 Pages) RENESAS

39 / 836 page

Section 1 Overview

Rev. 5.00 Mar. 15, 2007 Page 1 of 794

REJ09B0237-0500

Section 1 Overview

This LSI is a CMOS single-chip microcontroller that integrates a Renesas Technology original

RISC (Reduced Instruction Set Computer) CPU core with peripheral functions required for an

Ethernet system.

The CPU of this LSI has a RISC (Reduced Instruction Set Computer) type instruction set. The

CPU basically operates at a rate of one instruction per cycle, offering a great improvement in

instruction execution speed. In addition, the 32-bit internal architecture provides improved data

processing power. With this CPU, it has become possible to assemble low-cost and high-

performance/high-functionality systems even for applications such as realtime control, which

could not previously be handled by microcontrollers because of their high-speed processing

requirements.

This LSI is equipped with an Ethernet controller that includes a media access controller (MAC)

conforming to the IEEE802.3u standard and a physical layer transceiver (PHY), enabling 10/100

Mbps LAN connection. As the equipped Ethernet controller also includes a media independent

interface (MII) standard unit, a PHY LSI can be externally connected.

In addition, this LSI provides on-chip peripheral functions necessary for system configuration,

such as cache memory, RAM, a direct memory access controller (DMAC), timers, a serial

communication interface with FIFO (SCIF), a serial IO with FIFO (SIOF), a host interface (HFI),

an interrupt controller (INTC), and I/O ports.

The external memory access support function of this LSI enables direct connection to various

types of memory, such as standard memory, SDRAM, and PCMCIA. This greatly reduces system

cost.

SH7619 Datasheet(PDF) 39 Page - Renesas Technology Corp