SH7050 datasheet(49/841 Pages) RENESAS

49 / 841 page

Section 2 CPU

Rev. 5.00 Jan 06, 2006 page 29 of 818

REJ09B0273-0500

2.3.2

Addressing Modes

Table 2.8 describes addressing modes and effective address calculation.

Table 2.8

Addressing Modes and Effective Addresses

Addressing

Mode

Instruction

Format

Effective Addresses Calculation

Equation

Direct register

addressing

The effective address is register Rn. (The operand

is the contents of register Rn.)

—

Indirect register

addressing

@Rn

The effective address is the content of register Rn.

Post-increment

indirect register

addressing

@Rn+

The effective address is the content of register Rn.

A constant is added to the content of Rn after the

instruction is executed. 1 is added for a byte

operation, 2 for a word operation, and 4 for a

longword operation.

1/2/4

Rn + 1/2/4

(After the

instruction

executes)

Byte: Rn + 1

→ Rn

Word: Rn + 2

→ Rn

Longword:

Rn + 4

→ Rn

Pre-decrement

indirect register

addressing

@–Rn

The effective address is the value obtained by

subtracting a constant from Rn. 1 is subtracted for

a byte operation, 2 for a word operation, and 4 for

a longword operation.

1/2/4

Rn – 1/2/4

–

Rn – 1/2/4

Byte: Rn – 1

→ Rn

Word: Rn – 2

→ Rn

Longword:

Rn – 4

→ Rn

(Instruction

executed with

Rn after

calculation)

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