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SH7050 Datasheet(PDF) 55 Page - Renesas Technology Corp

Part # SH7050
Description  32-Bit RISC Microcomputer SuperH RISC engine Family/
PDF  841 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7050 Datasheet(HTML) 55 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 5.00 Jan 06, 2006 page 35 of 818
REJ09B0273-0500
Instruction Formats
Source
Operand
Destination
Operand
Example
d format
dddd
xxxx
15
0
xxxx
dddd
dddddddd:
Indirect GBR
with
displacement
R0 (Direct
register)
MOV.L
@(disp,GBR),R0
R0(Direct
register)
dddddddd:
Indirect GBR with
displacement
MOV.L
R0,@(disp,GBR)
dddddddd: PC
relative with
displacement
R0 (Direct
register)
MOVA
@(disp,PC),R0
—
dddddddd: PC
relative
BF
label
d12 format
dddd
xxxx
15
0
dddd
dddd
—
dddddddddddd:
PC relative
BRA
label
(label = disp +
PC)
nd8 format
dddd
nnnn
xxxx
15
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
iiiiiiii: Immediate
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
i format
xxxx
xxxx
i i i i
15
0
i i i i
iiiiiiii: Immediate
R0 (Direct
register)
AND
#imm,R0
iiiiiiii: Immediate
—
TRAPA
#imm
ni format
nnnn
i i i i
xxxx
15
0
i i i i
iiiiiiii: Immediate
nnnn: Direct
register
ADD
#imm,Rn
Note:
*
In multiply/accumulate instructions, nnnn is the source register.



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