SH7050 datasheet(31/841 Pages) RENESAS

31 / 841 page

Section 1 Overview

Rev. 5.00 Jan 06, 2006 page 11 of 818

REJ09B0273-0500

Type

Symbol

Pin No.

I/O

Name

Function

Interrupts

IRQOUT

159

Output

Interrupt

request

output

Indicates that an interrupt has

been generated.

Enables interrupt generation

to be recognized in the bus-

released state.

Address bus

A0–A21

17–20, 22,

24–28, 30,

32–36, 38,

40–44

Output

Address bus

Address output pins.

Data bus

D0–D15

85–88, 90,

92–96, 98,

100–104

Input/

output

Data bus

16-bit bidirectional data bus

pins.

Bus control

CS0–CS3

52–54, 133

Output

Chip select

0 to 3

Chip select signals for

external memory or devices.

Output

Read

Indicates reading from an

external device.

WRH

Output

Upper write

Indicates writing of the upper

8 bits of external data.

WRL

Output

Lower write

Indicates writing of the lower

8 bits of external data.

WAIT

Input

Wait

Input for wait cycle insertion

in bus cycles during external

space access.

DREQ0–

DREQ1

131, 128

Input

DMA transfer

request

(channels 0, 1)

Input pin for external requests

for DMA transfer.

Direct memory

access

controller

(DMAC)

DRAK0–

DRAK1

61, 62

Output

DREQ request

acknowledg-

ment (channels

0, 1)

These pins output the input

sampling acknowledgment for

external requests for DMA

transfer.

DACK0–

DACK1

129, 127

Output

DMA transfer

strobe

(channels 0, 1)

These pins output a strobe to

the external I/O of external

DMA transfer requests.

SH7050 Datasheet(PDF) 31 Page - Renesas Technology Corp

SH7050 Datasheet(HTML) 31 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL