SH7050 datasheet(12/841 Pages) RENESAS

12 / 841 page

Rev. 5.00 Jan 06, 2006 page xii of xx

10.2.19 Duty Registers (DTR) .......................................................................................... 282

10.3

Operation .......................................................................................................................... 283

10.3.1 Overview.............................................................................................................. 283

10.3.2 Free-Running Count Operation and Cyclic Count Operation .............................. 285

10.3.3 Output Compare-Match Function ........................................................................ 286

10.3.4 Input Capture Function ........................................................................................ 288

10.3.5 One-Shot Pulse Function ..................................................................................... 289

10.3.6 Offset One-Shot Pulse Function .......................................................................... 290

10.3.7 Interval Timer Operation ..................................................................................... 292

10.3.8 Twin-Capture Function ........................................................................................ 294

10.3.9 PWM Timer Function .......................................................................................... 295

10.3.10 Buffer Function.................................................................................................... 297

10.3.11 One-Shot Pulse Function Pulse Output Timing ................................................... 298

10.3.12 Offset One-Shot Pulse Function Pulse Output Timing ........................................ 299

10.3.13 Channel 3 to 5 PWM Output Waveform Actual Cycle and Actual Duty ............ 300

10.3.14 Channel 3 to 5 PWM Output Waveform Settings and Interrupt Handling

Times ................................................................................................................... 301

10.3.15 PWM Output Operation at Start of Channel 3 to 5 Counter ................................ 303

10.3.16 PWM Output Operation at Start of Channel 6 to 9 Counter ................................ 304

10.3.17 Timing of Buffer Register (BFR) Write and Transfer by Buffer Function .......... 305

10.4

Interrupts ........................................................................................................................... 306

10.4.1 Status Flag Setting Timing................................................................................... 306

10.4.2 Interrupt Status Flag Clearing .............................................................................. 311

10.5

CPU Interface.................................................................................................................... 313

10.5.1 Registers Requiring 32-Bit Access ...................................................................... 313

10.5.2 Registers Requiring 16-Bit Access ...................................................................... 314

10.5.3 8-Bit or 16-Bit Accessible Registers.................................................................... 315

10.5.4 Registers Requiring 8-Bit Access ........................................................................ 316

10.6

Sample Setup Procedures.................................................................................................. 316

10.7

Usage Notes ...................................................................................................................... 329

10.8

Advanced Timer Unit Registers And Pins ........................................................................ 343

Section 11 Advanced Pulse Controller (APC) ............................................................ 345

11.1

Overview........................................................................................................................... 345

11.1.1 Features................................................................................................................ 345

11.1.2 Block Diagram ..................................................................................................... 346

11.1.3 Pin Configuration................................................................................................. 347

11.1.4 Register Configuration......................................................................................... 347

11.2

Register Descriptions ........................................................................................................ 348

11.2.1 Pulse Output Port Control Register (POPCR)...................................................... 348

11.3

Operation .......................................................................................................................... 349

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