7641 datasheet(75/385 Pages) RENESAS

75 / 385 page

Rev.2.00

Aug 28, 2006

page 58 of 113

7641 Group

REJ09B0336-0200

HARDWARE

FUNCTIONAL DESCRIPTION

[USB endpoint x (x = 0 to 4) OUT Write Count Registers (Low

and High)] WRT_CNTRL, WRT_CNTH

These registers contain the number of bytes in the endpoint x

OUT FIFO. These are read-only registers. These two registers

must be read after the USB FCU has received a packet of data

from the host. When reading these registers, the lower byte must

be read first, then the higher byte.

When the OUT FIF0 is in double buffer mode, the CPU first reads

the received number of bytes of the former data packet. The next

CPU read can obtain that of the new data packet.

Fig. 51 Structure of USB endpoint x (x = 0 to 4) OUT write count registers

Low-order 8 bits of the number of bytes in endpoint x OUT FIFO

USB endpoint x OUT write count register Low (address 005D16)

WRT_CNTL

High-order 2 bits of the number of bytes in endpoint x OUT FIFO

Not used (“0” at read)

USB endpoint x OUT write count register High (address 005E16)

WRT_CNTH

[USB Endpoint x (x = 0 to 4) FIFO Register] USBFIFOx

These registers are the USB IN (transmit) and OUT (receive) FIFO

data registers. Write data to the corresponding register, and read

data from the corresponding register.

When the maximum packet size is equal to or less than half the

FIFO size, these registers function in double buffer mode and can

hold two packets of data. When the IN_PKT_RDY bit is “0” and

the TX_NOT_EMPTY bit is “1”, these bits indicate that one packet

of data is stored in the IN FIFO. When the OUT FIFO is in double

buffer mode, the OUT_PKT_RDY flag remains as “1” after the first

packet of data is read out (it actually goes to “0” and returns to “1”

after one

φ cycle).

Endpoint x IN/OUT FIFO

USB endpoint x FIFO register

(addresses 006016, 006116, 006216, 006316, 006416,)

USBFIFOx

Fig. 52 Structure of USB endpoint x (x = 0 to 4) FIFO register

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