7641 datasheet(12/385 Pages) RENESAS

12 / 385 page

Rev.2.00

Aug 28, 2006

page 8 of 13

7641 Group

REJ09B0336-0200

Fig. 2.5.13 Timing chart for cycle steal transfer caused by hardware-related transfer request

..................................................................................................................................... 93

Fig. 2.5.14 Timing chart for cycle steal transfer caused by software trigger transfer request

..................................................................................................................................... 93

Fig. 2.5.15 Timing chart for burst transfer caused by hardware-related transfer request .... 94

Fig. 2.5.16 Setting of relevant registers (1) ................................................................................ 96

Fig. 2.5.17 Setting of relevant registers (2) ................................................................................ 97

Fig. 2.5.18 Control procedure ........................................................................................................ 98

Fig. 2.7.1 Memory map of registers related to frequency synthesizer .................................. 101

Fig. 2.7.2 Structure of CPU mode register A ........................................................................... 102

Fig. 2.7.3 Structure of Frequency synthesizer control register .............................................. 102

Fig. 2.7.4 Structure of Frequency synthesizer multiply register 1 ......................................... 103

Fig. 2.7.5 Structure of Frequency synthesizer multiply register 2 ......................................... 103

Fig. 2.7.6 Structure of Frequency synthesizer divide register ................................................ 104

Fig. 2.7.7 Block diagram for frequency synthesizer circuit ..................................................... 105

Fig. 2.7.8 Frequency synthesizer multiply register 2 setting example .................................. 105

Fig. 2.7.9 Frequency synthesizer multiply register 1 setting example .................................. 106

Fig. 2.7.10 Frequency synthesizer divide register setting example ....................................... 106

Fig. 2.8.1 Memory map of registers related to master CPU bus interface .......................... 108

Fig. 2.8.2 Structure of Data bus buffer register x (x = 0, 1) ................................................. 109

Fig. 2.8.3 Structure of Data bus buffer status register x (x = 0, 1) ...................................... 109

Fig. 2.8.4 Structure of Data bus buffer control register 0 ...................................................... 110

Fig. 2.8.5 Structure of Data bus buffer control register 1 ...................................................... 110

Fig. 2.8.6 Connection example .................................................................................................... 112

Fig. 2.8.7 Setting of relevant registers ...................................................................................... 114

Fig. 2.8.8 Control procedure ........................................................................................................ 115

Fig. 2.9.1 Memory map of registers related to special count source generator .................. 116

Fig. 2.9.2 Structure of Special count source generator 1 ....................................................... 117

Fig. 2.9.3 Structure of Special count source generator 2 ....................................................... 117

Fig. 2.9.4 Structure of Special count source mode register ................................................... 118

Fig. 2.10.1 Memory map of registers related to external devices connection ..................... 120

Fig. 2.10.2 Structure of CPU mode register A ......................................................................... 121

Fig. 2.10.3 Structure of CPU mode register B ......................................................................... 121

Fig. 2.10.4 Software wait timing example ................................................................................. 123

Fig. 2.10.5 RDY wait timing example ......................................................................................... 124

Fig. 2.10.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example

.................................................................................................................................... 125

Fig. 2.10.7 Hold function timing diagram ................................................................................. 126

Fig. 2.10.8 Connection example of memory access up to 256 Kbytes ................................ 127

Fig. 2.10.9 External ROM and RAM example ........................................................................... 128

Fig. 2.10.10 RDY function use example .................................................................................... 129

Fig. 2.10.11 Read cycle (OE access, SRAM) ........................................................................... 130

Fig. 2.10.12 Read cycle (OE access, EPROM) ........................................................................ 130

Fig. 2.10.13 Write cycle (W control, SRAM) ............................................................................. 131

Fig. 2.11.1 RAM backup system ................................................................................................. 134

Fig. 2.12.1 Memory map of registers related to clock generating circuit ............................. 135

Fig. 2.12.2 Structure of CPU mode register A ......................................................................... 136

Fig. 2.12.3 Structure of Clock control register .......................................................................... 136

Fig. 2.12.4 Structure of Frequency synthesizer control register ............................................ 137

Fig. 2.12.5 Structure of Frequency synthesizer multiply register 1 ....................................... 137

Fig. 2.12.6 Structure of Frequency synthesizer multiply register 2 ....................................... 138

Fig. 2.12.7 Structure of Frequency synthesizer divide register .............................................. 138

List of figures

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