7641 datasheet(17/385 Pages) RENESAS

17 / 385 page

Rev.2.00

Aug 28, 2006

page 13 of 13

7641 Group

REJ09B0336-0200

Table 3.1.7 Master CPU bus interface (MBI; R/W type) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta

= –20 to 70°C, unless otherwise noted) ................................................................ 7

Table 3.1.8

Timing requirements and switching characteristics in memory expansion and

microprocessor modes (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C,

unless otherwise noted) ............................................................................................ 8

Table 3.1.9 Recommended operating conditions (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to

70°C, unless otherwise noted) .............................................................................. 10

Table 3.1.10 Electrical characteristics (1) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta =

–20 to 70°C, unless otherwise noted) ................................................................. 11

Table 3.1.11 Electrical characteristics (2) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C,

unless otherwise noted) ......................................................................................... 12

Table 3.1.12 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless

otherwise noted) ...................................................................................................... 13

Table 3.1.13 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 3.0 to 3.6 V, Vss

= 0 V, Ta = –20 to 70°C, unless otherwise noted) ........................................... 14

Table 3.1.14 Master CPU bus interface (MBI; R/W type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta

= –20 to 70°C, unless otherwise noted) ............................................................. 14

Table 3.1.15

Timing requirements and switching characteristics in memory expansion and

microprocessor modes (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless

otherwise noted) ...................................................................................................... 15

Table 3.3.1 Bits of which state might be changed owing to software write ......................... 35

List of tables

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