7641 datasheet(320/385 Pages) RENESAS

320 / 385 page

Rev.2.00

Aug 28, 2006

page 41 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.3 Notes on use

➁ How to reference the processor status register

To reference the contents of the processor status register (PS), execute the PHP instruction once

then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its

original status. A NOP instruction should be executed after every PLP instruction.

Be sure to execute the SEI instruction before the PLP instruction. If executing the CLI instruction,

do it after the NOP instruction

Fig. 3.3.7 Stack memory contents after PHP

instruction execution

Fig. 3.3.6 Sequence of PLP instruction execution

PLP instruction execution

↓

NOP

(S)

(S)+1

Stored PS

(2) BRK Instruction

It can be detected that the BRK instruction interrupt event or the least priority interrupt event by

referring the stored B flag state. Refer to the stored B flag state in the interrupt routine.

(3) Decimal Calculations

When decimal mode is selected, the values of the V flags are invalid.

The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to

“0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag

must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized

to “1” before each calculation.

(4) Multiplication and Division Instructions

The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.

(5) Instruction Execution Time

The instruction execution time is obtained by multiplying the frequency of the internal clock

φ by the

number of cycles needed to execute an instruction.

The number of cycles required to execute an instruction is shown in the list of machine instructions.

7641 Datasheet(PDF) 320 Page - Renesas Technology Corp