SH7018 datasheet(339/431 Pages) RENESAS

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16.4

The registers used to control the on-chip flash memory when enabled are shown in table 16.2.

Table 16.2

Flash Memory Registers

Abbreviation

R/W

Initial Value

Address

Access Size

Flash memory control

FLMCR1

R/W*

H'00*

H'FFFF8580

Flash memory control

FLMCR2

H'00

H'FFFF8581

Erase block register 1

EBR1

R/W*

H'00*

H'FFFF8582

Erase block register 2

EBR2

R/W*

H'00*

H'FFFF8583

RAM emulation register

RAMER

R/W

H'0000

H'FFFF8628

8, 16, 32

Notes: 1. Writes are disabled when the FWE bit is set to 1 in FLMCR1.

2. When a low level is input to the FWP pin, the initial value is H'80.

3. When a high level is input to the FWP pin, or if a low level is input and the SWE bit in

FLMCR1 is not set, these registers are initialized to H'00.

4. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers, and RAMER is a 16-bit

5. Only byte accesses are valid for FLMCR1, FLMCR2, EBR1, and EBR2, the access

requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and

6 cycles for a longword access.

6. When a longword write is performed on RAMER, 0 must always be written to the lower

word (address H'FFFF8630). Operation is not guaranteed if any other value is written.

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