SH7018 datasheet(393/431 Pages) RENESAS

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18.2

Standby Control Register (SBYCR)

The standby control register (SBYCR) is a read/write 8-bit register that sets the transition to

standby mode, and the port status in standby mode. The SBYCR is initialized to H'1F when reset.

Bit:

SBY

HIZ

—

Initial value:

R/W:

R/W

• Bit 7—Standby (SBY): Specifies transition to the standby mode. The SBY bit cannot be set to

1 while the watchdog timer is running (when the timer enable bit (TME) of the WDT timer

control/status register (TCSR) is set to 1). To enter the standby mode, always halt the WDT by

0 clearing the TME bit, then set the SBY bit.

Bit 7: SBY

Description

Executing SLEEP instruction puts the LSI into sleep mode

(Initial value)

Executing SLEEP instruction puts the LSI into standby mode

• Bit 6—Port High Impedance (HIZ): In the standby mode, this bit selects whether to set the I/O

port pin to high impedance or hold the pin status. The HIZ bit cannot be set to 1 when the TME

bit of the WDT timer control/status register (TCSR) is set to 1. When making the I/O port pin

status high impedance, always clear the TME bit to 0 before setting the HIZ bit.

Bit 6: HIZ

Description

Holds pin status while in standby mode

(Initial value)

Keeps pin at high impedance while in standby mode

• Bits 5 to 0—Reserved: Bit 5 is always reads as 0. The write value should always be 0. Bits 4 to

0 are always read as 1. The write value should always be 0.

18.3

Sleep Mode

18.3.1

Transition to Sleep Mode

Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the

program execution state to the sleep mode. Although the CPU halts immediately after executing

the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip

peripheral modules continue to run during the sleep mode.

SH7018 Datasheet(PDF) 393 Page - Renesas Technology Corp