SH7018 datasheet(392/431 Pages) RENESAS

392 / 431 page

376

Table 18.1

Power-Down State Conditions

State

Mode

Entering

Procedure

Clock CPU

On-Chip

Peripheral

Modules

CPU

Registers RAM

I/O

Ports

Canceling

Procedure

Sleep

Execute SLEEP

instruction with

SBY bit set to 0

in SBYCR

Run

Halt

Run

Held

• Interrupt

• DMAC

address error

• Power-on

reset

Stand-

Execute SLEEP

instruction with

SBY bit set to 1

in SBYCR

Halt

Halt*

Held

Held or

high

impe-

dance*

• NMI interrupt

• Power-on

reset

SBYCR: standby control register.

SBY: standby bit

Notes: 1. Some bits within on-chip peripheral module registers are initialized by the standby

mode; some are not. Refer to table 18.3, Register States in the Standby Mode, in

section 18.4.1, Transition to Standby Mode. Also refer to the register descriptions for

each peripheral module.

2. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of

the SBYCR. Refer to section 18.2, Standby Control Register (SBYCR). For pin status

other than for the I/O port, refer to Appendix B, Pin Status.

18.1.2

Related Register

Table 18.2 shows the register used for power-down state control.

Table 18.2

Related Register

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Standby control register

SBYCR

R/W

H'1F

H'FFFF8614

8, 16, 32

SH7018 Datasheet(PDF) 392 Page - Renesas Technology Corp

SH7018 Datasheet(HTML) 392 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL